1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a duty cycle correction circuit used in a semiconductor memory apparatus.
2. Related Art
A semiconductor memory apparatus receives a clock from an outside and operates in synchronization with the inputted clock. If the duty of the clock inputted from the outside is inaccurate, it is difficult for the semiconductor memory apparatus to operate normally. Thus, in order to prevent a situation where the duty of the clock inputted from the outside becomes inaccurate, a circuit for correcting the duty of the clock is designed and used in the semiconductor memory apparatus. In general, the circuit for correcting the duty of the clock in the semiconductor memory apparatus is called a duty cycle correction circuit.
As a semiconductor memory apparatus operates at a high speed, a high frequency external clock is inputted. In this regard, in order to ensure the stable operation of the semiconductor memory apparatus operating at a high speed, it is necessary to secure operational stability of a duty cycle correction circuit for correcting the duty ratio of the clock. Also, in order to accommodate the trend toward low power consumption and high areal efficiency of a semiconductor memory apparatus, a duty cycle correction circuit capable of reducing power consumption and having improved areal efficiency has been demanded in the art.